Common Errors in Your PCB Design

Dated:2017-09-06      Popularity:1308

When designing the PCB board, it is common to meet some challenges and make some errors. In this article, we list some frequent PCB design errors you should avoid. 

Automatic Wiring

Error 1: The requirement for this PCB board is simple, so it is ok to use some fine wire and automatically layout it.
Remark: Automatic wiring is bound to use a larger PCB area, while producing more through holes than manual wiring. For mass production, wire width and the number of through holes are included when considering cost factors by PCB manufacturers, because they affect the yield of finished PCB board and the number of consumed bits. To save the cost, you’d better manual wiring for your circuit board.

Error 2: It is better to pull the bus signal with resistors.
Remark: It is complicated to explain why the signal needs to be pulled, but you should remember not each signal needs to be pulled. The current used to pull a simple input signal is below several tens of microamps, but the current used to pull a driven signal will reach a milliampere level. The current system is often 32 bits of address data, possibly covering 244/245 isolated bus signal or other signal. If each is be pulled, then a few watts of power are consumed on these resistors.

Error 3: How to deal with the unused I/O port in CPU OR FPGA? Just leave it there.
Remark: If just leave the unused I/O port, then even a little bit of interference can be the input signal of repeated oscillation, however, the power consumption of MOS device basically depends on the number of turnouts of the gate circuit. If pull it up, then each pin will have a microampere level current, so the best way is to set it as the output.

Error 4: You can design as you like with the left FPGA.
Remark: The power consumption of the FGPA is proportional to the number of used triggers and the number of flip times, so the power consumption almost have 100 times’ difference in different circuits even used the same type of FPGA. The fundamental way to reduce the FPGA power consumption is possibly to minimize the number of flip flops for high speed flipping.

To be continued...

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