Ways to Avoid Embedded PCB ECOs
Engineering change orders (ECOs) not only will drive up design costs but also can cause numerous delays in product development that in turn lead to costly extension of time to market. Fortunately, most ECOs can be avoided by paying careful attention to seven critical areas where problems frequently occur: component selection, memory, moisture sensitivity levels (MSL), design for test (DFT), cooling methodologies, heat sinks, and coefficient of thermal expansion (CTE).
The same principles hold true for memory selection. With the constant emergence of new generations of more advanced DRAMs and flash, the PCB designer is challenged to stay ahead of the technology curve and determine how ever-changing memory specs affect newer designs.
Moisture Sensitivity Level
Moisture sensitivity level (MSL) is easily ignored. If an OEM doesn’t factor in MSL in a design and the critical MSL specifications aren’t properly called out, then there is a possibility that the CM house won’t take the MSL information into account and circuitry will not work properly in the field. This is especially true if MSL levels like 3, 4, or 5 exist. As a result, baking might not be properly performed and moisture might creep in, resulting in ECOs. Where LGAs are involved, the PCB assembly house will have to replace those packages on the PCBs.
Design for Test
Design for test (DFT) is critical for production runs when PCBs undergo test and debug. When placing components on a board, it is important to pay close attention to the placement of DFT probing points and the angle at which the probe comes in to touch vias, pads, and other test points. When DFT has not been allowed for early in the initial design, testing becomes a major issue and ECOs are generated. In some extreme cases, a re-spin is required to address the issue because ECOs may not work.
To be continued...